A technology for three-dimensionally arranging memory cells is proposed in, for instance, JP-A 2007-266143. In this technology, a plurality of conductive layers functioning as control gates in a memory device are stacked alternately with insulating layers to form a stacked body. Memory holes are formed therein, and a charge storage layer is formed on the inner wall of the memory hole. Then, silicon is provided in the memory hole. This technology provides a configuration in which the conductive layers cover the columnar silicon at prescribed intervals and a memory cell is formed at the intersection of each of the conductive layers and the silicon pillar. Stacking a large number of conductive layers enables a large memory capacity.
In the case where the number of stacked layers of the stacked body increases, the aspect ratio of a contact hole that pierces the stacked body to reach the substrate increases. It causes an increase in the difficulty level of the processing for the contact hole formation.